Tips for debugging the Launchpad G2 SPI communication

Tips for debugging the Launchpad G2 SPI communication
Qingfeng Xia at AMC ,the university of strathclyde
Tested on Launchpad MSP430 G2553

SPI is harder to debug error than the RS232 Serial port, there is no handy soft and hard wara such as realterm and COM port to debug the SPI communication.
(1) Read the MSP430 manual carefully and thoroughly.
There is significant different between the USART and new UCSI module, e.g. the controlling registers are different .

(2) Copy an simple and correct timer example, and test it, make sure MSP430 is working (not burned), then Copy an simple and correct SPI example on your MCU model and board.

(3) Using oscilloscope to debug SPI communication
First of all, make sure you can find the clock sequence on pin SCLK Using the ‘step into’ debug mode, and check the register content Check the clock source setting register,
make sure SMCLK is selected for high speed .
(SPI clock will not clock if there is no SPI communication, so trigger is needed
UCA0STAT will set some bits if error occurs
check the spelling for UCMSB or UCMST

(4) Loopback check (connect MISO to MOSI on board for MCU)
TXBUF ->RXBUF, Using the ‘step into’ debug mode

(5) Disable interrupt
RXIFG is shared by UCSI_A0 and UCSI_B0, it may means the IFG need to clear in the receiving ISR.

(6) If all test has been done, then connect the SPI target
The target needs proper setting up to response the sync communication of SPI. Target SPI CPOL setting up,
only writing valid byte to target such as AD7730, can triggering target SPI output,

(7) Disable Low power mode
LPM2 LPM3 may turn off SMCLK depends on SMCLK source clock, e.g. if SmCLK comes form DCO, LPM3 will turn it off, it means in the ISR, SPI can not be used!!!

//***************************original
code****************************************
// MSP430G2xx3 Demo – USCI_A0, SPI 3-Wire Slave Data Echo
//
// Description: SPI slave talks to SPI master using 3-wire mode. Data received // from master is echoed back. USCI RX ISR is used to handle communication, // CPU normally in LPM4. Prior to initial data exchange, master pulses // slaves RST for complete reset.
// ACLK = n/a, MCLK = SMCLK = DCO ~1.2MHz
//
// Use with SPI Master Incremented Data code example. If the slave is in // debug mode, the reset signal from the master will conflict with slave’s // JTAG; to work around, use IAR’s “Release JTAG on Go” on slave device. If // breakpoints are set in slave RX ISR, master must stopped also to avoid // overrunning slave RXBUF.
//
// MSP430G2xx3 UCSI_A0
//

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